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74ALVCH16821DGG ECAD models PCB Symbol, Footprint & ECAD Model

20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State)

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates.

Each register is fully edge triggered. The state of each nDn input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s nQn output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74ALVCH16821DGG 74ALVCH16821DGGS 935259010512 SOT364-1 Order product
74ALVCH16821DGG 74ALVCH16821DGGY 935259010518 SOT364-1 Order product
74ALVCH16821DGG 74ALVCH16821DGG:11 935259010112 SOT364-1 Order product
74ALVCH16821DGG 74ALVCH16821DGG,11 935259010118 SOT364-1 Order product


  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low-power consumption
  • Direct interface with TTL levels
  • Current drive ± 24 mA at 3.0 V
  • MULTIBYTE flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • Output drive capability 50 Ω transmission lines at 85°C
  • All data inputs have bushold
  • Complies with JEDEC standard no. 8-1A
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V

Target applications


Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16821DGGProduction2.3 - 3.6TTL± 242.5350low-40~859321.0TSSOP56


Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
( 9352 590 10512 )
Tube in Drypack
( 9352 590 10518 )
ActiveALVCH16821Reel 13" Q1/T1 in Drypack

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFEFRIFRMTBF (hour)MSLMSL leadfree
Quality and reliability disclaimer

Documentation (5)

File nameTitleTypeDate
74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger; 3-stateData sheet2018-02-02
alvch16821alvch16821 IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT364-1_118TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyOutline drawing2018-10-18


If you are in need of design/technical support, let us know and fill in the answer form, we'll get back to you shortly.


File nameTitleTypeDate
alvch16821alvch16821 IBIS modelIBIS model2013-04-07

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74ALVCH16821DGG74ALVCH16821DGGS935259010512Tube in DrypackOrder product
74ALVCH16821DGG74ALVCH16821DGGY935259010518Reel 13" Q1/T1 in DrypackOrder product
74ALVCH16821DGG74ALVCH16821DGG:11935259010112Bulk PackOrder product
74ALVCH16821DGG74ALVCH16821DGG,11935259010118Reel 13" Q1/T1Order product


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