74LVC573ABQ PCB Symbol, Footprint & ECAD Model

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V or 5 V applications.

The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin arrangement.

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

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Features

5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High impedance when V_CC = 0 V
Flow-through pin-out architecture
Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBMJESD22-A114F exceeds 2000 V
- MM JESD22-A115-B exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74LVC573ABQ	Production	1.2 - 3.6	TTL	± 24	3.4	8	low	-40~125	79	9.5	50	DHVQFN20

Package

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Outline version	Reflow-/Wave soldering	Packing
74LVC573ABQ	74LVC573ABQ,115 ( 9352 735 07115 )	Active	LVC573A	DHVQFN20 (SOT764-1)	SOT764-1		Reel 7" Q1/T1

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	RoHS / RHF	EFR	IFR	MTBF (hour)	MSL	MSL leadfree
74LVC573ABQ	74LVC573ABQ,115	74LVC573ABQ		123.8	3.87	2.58E8	1	1

Quality and reliability disclaimer

Series

74LVC573A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

Documentation (6)

File name	Title	Type	Date
74LVC573A	Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state	Data sheet	2018-09-26
AN11009	Pin FMEA for LVC family	Application note	2019-01-09
lvc573a	lvc573a IBIS model	IBIS model	2013-04-07
lvc	lvc Spice model	SPICE model	2013-05-06
SOT764-1_115	DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or X Ordering code (12NC) ending 115	Packing	2013-04-23
SOT764-1	plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm body	Outline drawing	2018-11-14

Support

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Models

File name	Title	Type	Date
lvc573a	lvc573a IBIS model	IBIS model	2013-04-07
lvc	lvc Spice model	SPICE model	2013-05-06

Ordering, pricing & availability

Type number	Orderable part number	Ordering code (12NC)	Packing	Buy online
74LVC573ABQ	74LVC573ABQ,115	935273507115	Reel 7" Q1/T1	Order product

Sample

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